This invention relates to capacitors formed in integrated circuits (ICs). More particularly, the present invention relates to a new and improved encapsulated metal vertical interdigitated capacitor located between interconnect layers of an IC, and a damascene method of making the same. The capacitor construction allows highly conductive metal, such as copper, to be used as conductors in the interconnect layers and to contact the plates of the capacitor while deterring metal atom diffusion or metal ion migration which may occur under elevated temperature conditions or biasing conditions and to prohibit and to prevent adverse effects from such migration, among other things. The damascene method of manufacturing the capacitor avoids difficult-to-execute etching steps which would otherwise be required to fabricate the capacitor and the IC while simultaneously avoiding residual accumulations of material in openings following chemical mechanical polishing steps required to form the multiple interconnect layers, among other things.
Modern integrated circuits (ICs) are frequently constructed using multiple layers or levels of electrical conductors formed above a substrate into which the functional devices of the IC are formed. Each level of electrical conductors is referred to as an xe2x80x9cinterconnect layer.xe2x80x9d Multiple interconnect layers are advantageous in ICs because valuable substrate space is not excessively consumed by the electrical connections between the various components. Instead, the electrical conductors of each interconnect layer route the signals between many of the functional components in the substrate. The ability to construct ICs with multiple interconnect layers has come about as a result of planarization techniques such as chemical mechanical polishing (CMP).
In addition to routing the electrical signals by conductors outside the substrate, the interconnect layers have also been employed for additional beneficial functions, such as the incorporation of capacitors in interlayer dielectric (ILD) insulating material which separates the electrical conductors of the vertically separated interconnect layers, and the incorporation of capacitors with the conductors of the interconnect layers themselves. The above referenced U.S. patent applications all pertain to the incorporation of capacitors with the interconnect layers and to a technique for vertically orienting portions of the capacitor plates between the interconnect layers to maximize the amount of capacitance obtained relative to the horizontal surface area consumed.
The first two above referenced U.S. patent applications, xe2x80x9cVertically Interdigitated Metal-Insulator-Metal Capacitor for an Integrated Circuitxe2x80x9d and xe2x80x9cProcess for Fabricating Vertical Interdigitated Metal-Insulator-Metal Structure within an Integrated Circuitxe2x80x9d describe a capacitor structure and fabrication process which has the advantage of forming vertical plate capacitors between the interconnect layers using CMP process steps when openings in the structure are not present, thereby avoiding the accumulation of residual slurry material from the CMP process and resist material from the subsequent photolithographic process in the openings. Residual slurry material accumulated in the openings creates subsequent fabrication difficulties and defects in the resulting IC. For example, residual photoresist will outgas when metal is applied over it. The outgas effect prevents the metal from depositing properly, if at all. Inadequately deposited metal may result in open or unreliable circuit connections, thereby degrading the functionality of the IC or capacitor. Residual materials are extremely difficult to remove completely from the opening, and attempts to do so add additional process steps and may even raise the risk that the other existing circuit components will be damaged by the cleaning process itself.
The two applications mentioned in the preceding paragraph describe the inventions in the context of conventional aluminum electrical conductors in the interconnect layers and tungsten filling openings adjoining the upper capacitor plates and in via plug interconnects extending between the interconnect layers. Aluminum is typically used as a major component of the interconnect layer conductors because aluminum is relatively easily formed into desired conductor patterns by use of conventional photolithographic patterning and etching techniques. Etching aluminum can be effectively accomplished in a relatively low temperature environment. The low temperature environment does not introduce adverse influences on the other components of the IC. For example, relatively high temperatures may cause metal conductors to expand and deform, or the relatively high temperatures may cause metal grain growth which deforms the structure. Such adverse influences may destroy the components or reduce their functionality. Tungsten is used as the fill material for similar reasons and because of its compatibility with materials typically used in semiconductor processing.
Ideally, it would be more advantageous to use copper rather than aluminum for the conductors in the interconnect layer or tungsten as the fill material in the vias. Copper is more conductive than aluminum, thus allowing for less signal attenuation, smaller signal propagation delays and higher operating frequencies in the IC circuitry. However, plasma etching of copper in semiconductor fabrication requires a much higher temperature than the temperature required to plasma etch aluminum, thus causing the aforementioned temperature-induced adversities. At the present time there are no known cost-effective plasma etching techniques suitable for copper. Furthermore, atoms or ions of copper from copper conductors may diffuse or migrate throughout the insulating and other materials on the IC, including the substrate, and destroy the effectiveness of the functional devices and the insulators.
While it is known to encapsulate copper conductors in barrier metal to prevent or substantially inhibit the migration of the copper ions and the diffusion of copper atoms throughout the IC structure, such encapsulation techniques involve additional process steps and add complexity to the overall IC fabrication.
It is with regard to these and other considerations that the present invention has evolved.
One aspect of this invention relates to a relatively high capacity capacitor formed between interconnect layers which uses copper or other high conductivity metal conductors or metals capable of atom diffusion or ion migration in a manner in which capacitor plates serve as barrier metal to prevent the atom diffusion and migration of copper ions from high conductivity metal conductors throughout the IC. A related aspect of this invention relates to using barrier metal to at least partially encapsulate the high conductivity or copper conductors of the interconnect layers as well as a capacitor plate, thereby simplifying the IC construction by not requiring a full complement of separate steps to encapsulate the high conductivity or copper conductors. Another aspect of this invention relates to a capacitor construction and fabrication process in which the elements of the capacitor are formed by damascene processes and chemical metal polishing (CMP) processes, thereby avoiding the necessity to etch the copper or other high conductivity metal of the interconnect layer conductors and also avoiding the problems created from high temperature etching. A further aspect of this invention utilizes CMP and other planarization processes during the formation of the capacitor when openings are present, to continue to obtain the advantages of avoiding the accumulation of residual slurry materials in openings and of avoiding the necessity of additional cleaning steps during the IC fabrication process. Still a further aspect of this invention pertains to forming via plug interconnects between the conductors of the interconnect layers using the same high conductivity material of the interconnect layer conductors conjunctively with the formation of the capacitor while preventing metal atom diffusion and metal ion migration.
In accordance with these and other aspects, the present invention relates to an integrated circuit having an upper interconnect layer and a lower interconnect layer in which each interconnect layer comprises a conductor formed of a metal capable of atom diffusion or ion migration, such as copper. An improved capacitor is located between the upper and lower interconnect layers. The capacitor comprises upper and lower capacitor plates with capacitor dielectric material separating the plates. The lower plate has a portion contacting a conductor positioned within the lower interconnect layer and the upper plate has a portion contacting a conductor positioned within the upper interconnect layer. The portions of the upper and lower plates which contact the conductors form plate barrier layers to prevent atom diffusion and ion migration from the conductors at the contact locations.
Additionally, the present invention relates to a method of fabricating an integrated circuit (IC) having upper and lower interconnect layers between which a capacitor is located. The method comprising the steps of forming conductors in the interconnect layers of a metal capable of atom diffusion or ion migration within the IC, forming upper and lower capacitor plates having portions in contact with the conductors of the upper and lower interconnect layers, respectively, and forming the upper and lower capacitor plates of barrier metal to prevent atom diffusion and ion migration into the IC from the conductors at the locations contacted by the capacitor plate portions.
Additional preferred features of both the apparatus and method aspects of the invention relate to forming additional barrier layers contacting the conductors at locations other than where the capacitor plate portions contact the conductors to prevent atom diffusion and ion migration from the conductors at the other locations. The additional barrier layers are preferably formed of the same material as the material from which one of the plates is formed. In addition, the integrated circuit may include a via plug interconnect extending between conductors of the upper and lower interconnect layers, with a plug barrier layer surrounding the plug material to prevent atom diffusion and ion migration from the plug material. The plates of the capacitor may be oriented vertically to obtain maximum capacitance from a minimum amount of horizontal surface area. Preferably the capacitor plates are formed in U-shaped configurations. A finger portion of the interconnect layer conductor may project into the U-shaped portion of the upper capacitor plate. In addition, an additional finger portion of the interconnect layer conductor may project into a space adjoining the U-shaped lower capacitor plate to increase the amount of capacitance obtained.
A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detailed description of presently preferred embodiments of the invention, and to the appended claims.